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| P93U422 HIGH SPEED 256 x 4 STATIC CMOS RAM FEATURES Universal 256 x 4 Static RAM One part, the P93U422, replaces the following bipolar and CMOS parts: - 93422, 93422A - 93L422, 93L422A Fast Access Time - 35 ns Commercial and Military Available in the following packages: - PDIP, CERDIP, Side Brazed DIP - CERPACK - LCC - SOIC CMOS for Low Power - 440 mW (Commercial) - 495 mW (Military) 5V Power Supply 10% for both commercial and military temperature ranges Separate I/O Fully static operation with equal access and cycle times Resistant to single event upset and latchup due to advanced process and design improvements DESCRIPTION The P93U422 is a 1,024-bit high-speed Static RAM with a 256 x 4 organization. The P93U422 is a universal device designed to replace the entire 93 and 93L 256 x 4 static RAM families. The memory requires no clocks or refreshing and has equal access and cycle times. Inputs and outputs are fully TTL compatible. Operation is from a single 5 Volt supply. Easy memory expansion is provided by an active LOW chip select one (CS 1) and active HIGH chip select two (CS 2) as well as 3-state outputs. In addition to high performance, the device features latchup protection, single event and upset protection. The P93U422 is offered in several packages: 22-pin 400 mil DIP (plastic and ceramic), 24-pin 300 mil SOIC, 24-pin square LCC and 24-pin CERPACK. Devices are offered in both commercial and military temperature ranges. FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATIONS SOIC (S4) CERPACK (F3) DIP (P3-1, C3-1, D3-1) LCC (L4) Document # SRAM102 REV A 1 Revised October 2005 P93U422 MAXIMUM RATINGS(1) Symbol VCC Parameter Power Supply Pin with Respect to GND Terminal Voltage with Respect to GND (up to 7.0V) Operating Temperature Value - 0.5 to +7 - 0.5 to VCC +0.5 - 55 to +125 Unit V Symbol TBIAS TSTG I OUT Parameter Temperature Under Bias Storage Temperature DC Output Current Value - 55 to +125 - 65 to +150 20 Unit C C mA VTERM TA V C RECOMMENDED OPERATING CONDITIONS Grade(2) Commercial Military Ambient Temp 0C to 70C -55C to 125C Gnd 0V 0V Vcc 5.0V 10% 5.0V 10% CAPACITANCES(4) (VCC = 5.0V, TA = 25C, f = 1.0MHz) Symbol CIN COUT Parameter Input Capacitance Conditions Typ. Unit VIN = 0V 5 7 pF pF Output Capacitance VOUT = 0V DC ELECTRICAL CHARACTERISTICS Over recommended operating temperature and supply voltage(2) Symbol VOH VOL VIH VIL IIL IIH ISC ICC Parameter Output High Voltage Output Low Voltage Input High Level Input Low Level Input Low Current Input High Current Output Short Circuit Current (3) Power Supply Current VIN = 0.40 V VCC = Max, VIN = 4.5V VCC = Max., VOUT = 0.0V All Inputs = GND VCC = Max. IIN = -10mA VOUT = 2.4V, VCC = Max. VOUT = 0.5V, VCC = Max. -50 TA = 125C TA = 75C TA = 0C TA = -55C VCL ICEX Input Clamp Voltage Output Leakage Current Test Conditions VCC = Min., VIN = VIH or VIL, IOH = -5.2 mA VCC = Min., VIN = VIH or VIL, IOL = 8.0 mA 2.1 0.8 -300 40 -70 70 70 80 90 -1.5 50 V A mA 2.4 0.45 P93U422 Min. Max. Unit V V V V A A mA Notes: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM rating conditions for extended periods may affect reliability 2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds. 4. This parameter is sampled and not 100% tested. Document # SRAM102 REV A Page 2 of 10 P93U422 FUNCTIONAL DESCRIPTION An active LOW write enable (WE) controls the writing/ reading operation of the memory. When chip select one (CS 1) and write enable (WE) are LOW and chip select two (CS 2) is HIGH, the information on data inputs (D0 through D3) is written into the addressed memory word and preconditions the output circuitry so that true data is present at the outputs when the write cycle is complete. This preconditioning operation insures minimum write recovery times by eliminating the "write recovery glitch." Reading is performed with chip selct one (CS 1) LOW, chip select two (CS 2) HIGH, write enable (WE) HIGH and output enable (OE) LOW. The information stored in the addressed word is read out on the noninverting outputs (O0 through O3). The outputs of the memory go to an inactive high impedance state whenever chip select one (CS 1) is HIGH, or during the write operation when write enable (WE) is LOW. TRUTH TABLE Mode Standby Standby DOUT Disabled Read Write CS2 L X H H H CS 1 X H L L L WE X X X H L OE X X H L X Output High Z High Z High Z DOUT High Z Notes: H = HIGH L = Low X = Don't Care HIGH Z = Implies outputs are disabled or off. This condition is defined as high impedance state for the P93U422. SWITCHING CHARACTERISTICS (5,6) Over Operating Range (Commercial and Military) Parameters tPLH(A)(7) tPLH(A)(7) tPZH (CS1, CS2)(8) tPZL (CS1, CS2)(8) tPZH (WE)(8) tPZL (WE)(8) tPZH (OE)(8) tPZL (OE)(8) Description Delay from Address to Output (Address Access Time) (See Fig. 2) Delay from Chip Select to Active Output and Correct Data (See Fig. 2) Delay from Write Enable to Active Output and Correct Data (Write Recovery) (See Fig. 1) Delay from Output Enable to Active Output and Correct Data (See Fig. 2) Setup Time Address (Prior to Initiation of Write) (See Fig. 1) Hold Time Address (After Termination of Write) (See Fig. 1) Setup Time Data Input (Prior to Initiation of Write) (See Fig. 1) Hold Time Data Input (After Termination of Write) (See Fig. 1) Setup Time Chip Select (Prior to Initiation of Write) (See Fig. 1) Hold Time Chip Select (After Termination of Write) (See Fig. 1) Minimum Write Enable Pulse Width (to Insure Write) (See Fig. 1) P93U422 Min. Max. 35 25 25 25 5 5 5 5 5 5 20 30 30 30 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns tS(A) th(A) tS(DI) th(DI) tS (CS1, CS2) th (CS1, CS2) tpw(WE) tPHZ (CS1, CS2) tPLZ (CS1, CS2)(8) tPHZ (WE)(8) tPLZ (WE)(8) tPHZ (OE)(8) tPLZ (OE)(8) (8) Delay from Chip Select to Inactive Output (HIGH Z) (See Fig. 2) Delay from Write Enable to Inactive Output (HIGH Z) (See Fig. 1) Delay from Output Enable to Inactive Output (HIGH Z) (See Fig. 2) Document # SRAM102 REV A Page 3 of 10 P93U422 Notes: 5) Test conditions assume signal transition times of 10 ns or less. 6) Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 7) tPLH(A) and tPHL(A) are tested with S1 closed and CL = 15 pF with both input and output timing referenced to 1.5V 8) tPZH(WE), tPZH(CS1, CS2) and tPZH(OE) are measured with S1 open, CL = 15 pF and with both the input and output timing referenced to 1.5V. tPZL(WE), tPZL(CS1, CS2) and tPZL(OE) are measured with S1 closed, CL = 15pF and with both the input and output timing referenced to 1.5V. tPHZ(WE), tPHZ(CS1, CS2) and tPHZ(OE) are measured with S1 open, CL < 5pF and are measured between the 1.5V level input to the VOH -500mV level on the output. tPLZ(WE), tPLZ(CS1, CS2) and tPLZ(OE) are measured with S1 closed, CL < 5pF and are measured between the 1.5V level input to the VOL +500mV level on the output. on the on the SWITCHING TEST Test Circuits (7, 8) Document # SRAM102 REV A Page 4 of 10 P93U422 KEY TO DIAGRAM SWITCHING WAVEFORMS Write Mode (with OE = LOW) Figure 1. Read Mode Figure 2. Document # SRAM102 REV A Page 5 of 10 P93U422 ORDERING INFORMATION SELECTION GUIDE The P93U422 is available in the following temperature range, speed, and package options. Temperature Range Commercial Temperature Military Temperature Package Plastic DIP Plastic SOIC Side Brazed DIP CERDIP CERPACK LCC Side Brazed DIP Military Processed* CERDIP CERPACK LCC Speed (ns) 35 -35PC -35SC -35CM -35DM -35FM -35LM -35CMB -35DMB -35FMB -35LMB *Military temperature range with MIL-STD-883, Class B processing. Document # SRAM102 REV A Page 6 of 10 P93U422 Pkg # # Pins Symbol A b b2 C D E eA e L Q S1 S2 C3-1 22 (400 Mil) Min Max 0.200 0.014 0.026 0.035 0.060 0.008 0.015 1.100 0.360 0.410 0.400 BSC 0.100 BSC 0.125 0.200 0.015 0.060 0.005 0.005 - SIDE BRAZED DUAL IN-LINE PACKAGE Pkg # # Pins Symbol A b b2 C D E eA e L Q S1 D3-1 22 (400 Mil) Min Max 0.225 0.014 0.026 0.045 0.065 0.008 0.018 1.111 0.350 0.410 0.400 BSC 0.100 BSC 0.125 0.200 0.015 0.070 0.005 0 15 CERDIP DUAL IN-LINE PACKAGE Document # SRAM102 REV A Page 7 of 10 P93U422 Pkg # # Pins Symbol A b c D E e k L Q S S1 F3 24 Min Max 0.060 0.090 0.015 0.022 0.004 0.009 0.630 0.330 0.380 0.050 BSC 0.008 0.015 0.250 0.370 0.026 0.045 0.085 0.005 - CERPACK CERAMIC FLAT PACKAGE Pkg # # Pins Symbol A A1 B1 D/E D1/E1 D2/E2 D3/E3 e h j L L1 L2 ND NE L4 24 Min Max 0.060 0.075 0.050 0.065 0.022 0.028 0.395 0.410 0.250 BSC 0.125 BSC 0.410 0.050 BSC 0.040 REF 0.020 REF 0.045 0.055 0.045 0.055 0.075 0.095 6 6 SQUARE LEADLESS CHIP CARRIER Document # SRAM102 REV A Page 8 of 10 P93U422 Pkg # # Pins Symbol A A1 b b2 C D E1 E e eB L P3-1 22 (400 Mil) Min Max 0.210 0.015 0.014 0.022 0.045 0.065 0.009 0.015 1.065 1.120 0.330 0.390 0.390 0.425 0.100 BSC 0.500 0.115 0.160 0 15 PLASTIC DUAL IN-LINE PACKAGE Pkg # # Pins Symbol A A1 b2 C D e E H h L S4 24 (300 Mil) Min Max 0.093 0.104 0.004 0.012 0.013 0.020 0.009 0.012 0.598 0.614 0.050 BSC 0.291 0.299 0.394 0.419 0.010 0.029 0.016 0.050 0 8 SMALL OUTLINE IC PLASTIC PACKAGE Document # SRAM102 REV A Page 9 of 10 P93U422 REVISIONS DOCUMENT NUMBER: DOCUMENT TITLE: REV. ORIG A ISSUE DATE 1997 Oct-05 SRAM102 P93U422 HIGH SPEED 256 x 4 STATIC CMOS RAM ORIG. OF CHANGE DAB JDB DESCRIPTION OF CHANGE New Data Sheet Change logo to Pyramid Document # SRAM102 REV A Page 10 of 10 |
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